The present invention generally relates to a processing system wherein the processing system includes a peripheral device having a non-multiplexed interface and/or a peripheral device having a multiplexed interface. The present invention more particularly relates to a bus interface for use in a processing system of the time including a processor, such as a microprocessor or a microcontroller, to permit the processor to access either a non-multiplexed peripheral interface or a multiplexed peripheral interface without requiring additional external hardware to achieve both types of accesses.
In early processing systems, operating speed was not a critical requirement. As a result, the microprocessors of such early processing systems were arranged to operate in association with peripheral devices which included multiplexed interfaces. With such multiplexed interfaces, only eight external pins were required of the microprocessor for providing addresses and data during an access of the multiplexed peripheral interfaces. During a first phase of such an access, an eight-bit address is first provided from the eight pins to access, for example, a peripheral device internal register. When the eight-bit address is held by the processor, a latch within the multiplexed peripheral interface latches the eight-bit address responsive to an address latch enable signal from the microprocessor. After the eight-bit address is latched, and during a second access phase, either the microprocessor provides eight bits of data over the same eight pins for a write access or receives eight bits of data at the same eight pins from the multiplexed peripheral for a read access.
In more recent processing systems, operating speed has become a critical requirement. As a result, the microprocessors of such recent processing systems are arranged to operate in association with fast operating peripheral devices, such as memories, having non-multiplexed interfaces. These peripherals generally require addresses having sixteen bits and, by having non-multiplexed interfaces, are arranged to receive a sixteen bit address and to receive, for a write access, or provide, for a read access, eight bits of data during the same access phase. As a result, non-multiplexed peripheral devices can be accessed at a faster rate than multiplexed peripherals, although in accessing such non-multiplexed peripherals, twenty-four external pins are required of the processor for the addresses and data.
Since multiplexed peripheral devices have been in use for some time, their multiplexed configurations have become standardized. As a result, processing systems are often required to incorporate both multiplexed peripheral devices and non-multiplexed peripheral devices and provide the hardware necessary to permit the microprocessors of these systems to access both types of peripheral devices.
To that end, microprocessors are generally arranged for accessing only non-multiplexed peripheral interfaces and therefore, the processing systems require additional hardware, such as controllers external to the microprocessors, to permit accesses to multiplexed peripheral interfaces. This introduces intervening hardware which increases the cost of processing systems employing such hardware.